Abstract RFID is a technology that uses radio waves to transfer data from an electronic tag, called RFID tag or label, attached to an object, through a reader for the purpose of identifying and tracking objects. In addition sensory tag adds the additional external sensed data details in to the tag memory. Power consumption is one of the major issues in the RFID system. In passive tag, entire power for operation is drawn from the RFID reader as radio waves hence high power consumption of RFID tag reduce the reading range of the RFID system and hence performance degrades. Processor is the major component that consumes power. In existing system entire processor block is powered at all the time but it is not necessary. The proposed work targets on the digital section of the RFID tag processor based on EPC Class-1 Gen-2 protocol. Clock-Gating and Clock-management are the two hardware-level techniques for power saving in digital section. These techniques are employed via hardware circuit in the gen-2 processor to enable and disable the necessary operating blocks in the processor which minimize the power consumption of the processor and hence the RFID tag.