Abstract In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout. The methodology has been validated in a 0.18μm CMOS technology by sizing a number of opamp circuits targeting reasonably aggressive specification. In the examples it has been observed that SPICE simulation within ISGP methodology decreases error in some of the circuit parameters from 80% to less than 1% and that of some device parameters from 700% to less than 1%. For each example the design iteration converges rapidly within 7 iterations which take only 4mins using an Intel Core 2 Duo, 2.53GHz processor. Robustness of the final design points has been observed through PVT analysis and Monte Carlo simulation.