Abstract CMOS integrated circuits (ICs) operating in space or other radiation environments can suffer from three different reliability problems due to the radiation: total dose effects, dose rate effects, and single event effects. The two most significant total-dose reliability problems are subthreshold, gate, end-around leakage current and threshold voltage shift. This article documents the theory, design, implementation, and testing of new, second-layer polysilicon structures that can compensate for radiation-induced, subthreshold, gate, end-around, leakage current. Second-layer polysilicon is available in many commercial, bulk CMOS processes and is normally used for floating-gate devices, such as EEPROMs and FPLAs, and charge-coupled devices such as CCD focal plan arrays. The use of the described structures in CMOS ICs would allow radiation tolerant ICs to be fabricated with commercial, bulk CMOS processes, greatly reducing manufacturing costs when compared to the cost of fabricating ICs on dedicated, radiation-hardened process lines.