Publisher Summary To meet the stringent demands imposed on the memory system, new memory system architecture, the Fully Buffered DIMM, has been designed so that it can meet simultaneously the requirements of larger capacity and higher speed without needing new or expensive DRAM devices. The Fully Buffered DIMM replaces the conventional memory system bus topology with a narrow, point-to-point interface between the memory controller and the memory modules, enabling the use of a high data rate signaling system. The Fully Buffered DIMM memory system represents an intriguing attempt to meet the simultaneous demands placed on the memory system. This chapter examines the rationale used to justify the implementation and technical details of the Fully Buffered DIMM memory system. The FB-DIMM memory system also requires mechanisms for write data retry to protect against bit lane failures and to allow for the removal of faulting FB-DIMMs from a system and insertion of new FB-DIMMs into a system without powering down the entire system. A performance evaluation of the FB-DIMM memory system thus requires an in-depth understanding of the bandwidth and latency characteristics of the FB-DIMM memory system. Finally, studies are under way to examine possible extensions to the FB-DIMM-access protocol to allow for dynamic additive latency scheduling.