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Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options

Authors
Journal
Microelectronics Journal
0026-2692
Publisher
Elsevier
Publication Date
Volume
42
Issue
5
Identifiers
DOI: 10.1016/j.mejo.2011.01.004
Keywords
  • Asymmetric Double Gate Mosfet
  • Subthreshold Current Model
  • Subthreshold Swing Model
  • Back Gate Effects
  • Gate Underlap
  • Independent Gate (4T) Dgmosfet
  • Tied Gate (3T) Dgmosfet
Disciplines
  • Engineering

Abstract

Abstract Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

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