Affordable Access

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

IEEE Computer Society Press
Publication Date


A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation.

There are no comments yet on this publication. Be the first to share your thoughts.