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Efficient parallel multiplier in shifted polynomial basis

Authors
Journal
Journal of Systems Architecture
1383-7621
Publisher
Elsevier
Publication Date
Volume
53
Identifiers
DOI: 10.1016/j.sysarc.2006.09.004
Keywords
  • Binary Field
  • Parallel Multiplier
  • Shifted Polynomial Basis

Abstract

Abstract In this paper we study the multiplication in fields F 2 n using the Shifted Polynomial Basis (SPB) representation of Fan and Dai [H. Fan, Y. Dai, Fast bit-parallel GF(2 n ) multiplier for all trinomials, IEEE Transactions on Computers 54 (4) (2005) 485–490]. We give a simpler construction than in Fan and Dai (2005) of the matrix associated to the SPB used to perform the field multiplication. We present also a novel parallel architecture to multiply in SPB. This multiplier have a smaller time complexity (for good field it is equal to T A + ⌈log 2( n)⌉ T X ) than all previously presented architecture. For practical field F 2 n , i.e., for n ≅ 163, this roughly improves the delay by 10%. On the other hand the space complexity is increased by 25%: the space complexity is a little greater than the time gain.

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