Abstract Copper (Cu) replacing conventional tungsten (W) based 1st contact plug has become necessary for high performance CMOS. For a reliable and well optimized Cu plug, process selection and integration of plug diffusion barrier is an important task. In this work, we investigate barriers for Cu plug technology for CMOS process. Single layer TaN and bi-layer Ta + TaN barrier materials were studied for their effectiveness in preventing Cu diffusion into device active regions for backend thermal stress conditions. The degradation of device characteristics was used as monitor of robustness of barrier reliability. Diffusion of Cu in multilayer plug structure is modeled to explain observed stress behavior. From the model studies, the critical barrier layer thickness needed to prevent Cu diffusion is determined. We show than that a ∼7 nm sidewall barrier is effective in preventing Cu diffusion into Si at up to 350 °C/60 min only, while a minimum thickness of ∼10 nm is needed for blocking copper diffusion at 420 °C/30 min. Using multilayer Cu diffusion model, an optimized process window for reliable, low contact resistance Cu plug technology for CMOS process can be obtained.