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On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch

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IEEE Service Center
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  • Communication

Abstract

On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch Radu Stefan, Jason de Windt Computer Engineering Delft University of Technology Email: [email protected], [email protected] Kees Goossens Electronic Systems Eindhoven University of Technology Email: [email protected] Abstract—Networks-on-Chip are seen as a scalable solution for facilitating the development of Systems-on-Chip with an increasing number of IP cores. Many studies already address the implementation details of such networks and a large effort has been invested in optimizing the routing strategy and the organization of the network, however by comparison the interface between the network and the IPs has been largely ignored. In this study, we explore optimizations that can be performed at the layer that connects the IPs to the services offered by the NoC. In our FPGA prototype, a MicroBlaze soft-core is connected to a remote memory via the Æthereal NoC. By employing our optimizations to the interface between the MicroBlaze and the NoC, we demonstrate an improvement in terms of speed above 880% in memory intensive tests and of up to 12% in real life applications with little use of communication. I. INTRODUCTION The shrinking feature sizes in silicon technology allowed both an increase in the processing power and the number of IPs integrated on a single chip. At the same time consumer expectations adapt to the benefits provided by technology by both diversifying and demanding higher quality from already existing services. It is now customary for mobile phones for example to provide maps, route planning, gps and video capabilities. Building complex systems to support these features, pos- sibly integrating IPs from multiple vendors becomes then a difficult, time-consuming task. Employing networks-on-chip for connecting together the many IPs can significantly reduce the development effort [1], [2] and facilitate verification [3]. The reuse of interconnec

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