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Simulated fault injections and their acceleration in SystemC

Authors
Journal
Microprocessors and Microsystems
0141-9331
Publisher
Elsevier
Publication Date
Volume
32
Identifiers
DOI: 10.1016/j.micpro.2008.03.013
Keywords
  • Systemc
  • Simulated Fault Injection
  • Switch Level
  • Accelarated Simulation
Disciplines
  • Computer Science
  • Design

Abstract

Abstract SystemC has found a large acceptance for the description of electronic systems. An essential advantage of a SystemC description is the possibility of a built-in compiled-code simulation. Beyond the functional simulation for validation of a hardware design, there are additional requirements for an advanced simulation of faults in order to analyze the system behavior under fault conditions. The article introduces known and novel methods of SystemC-based simulations with fault injections and provides simulation results. Some strategies are shown to accelerate the SystemC simulation by parallel computing. Furthermore, we present gate level and switch level models for an effective simulation in SystemC.

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