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High-level parameterizable area estimation modeling for ASIC designs

Authors
Journal
Integration the VLSI Journal
0167-9260
Publisher
Elsevier
Volume
47
Issue
4
Identifiers
DOI: 10.1016/j.vlsi.2014.01.002
Keywords
  • Gate-Count Estimation
  • Architecture Exploration
  • Vlsi Circuits
  • Integrated Circuit Modeling
  • System-On-Chip
Disciplines
  • Astronomy
  • Communication
  • Design

Abstract

Abstract Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.

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