Enhancements of up to 100% in transconductance, mobility and on-current performance are demonstrated for p-MOSFET devices using strained-Si on virtual substrates of Si0.85Ge0.15 and Si0.8Ge0.2 compared to standard bulk silicon devices. A standard 0.25 µm high-thermal budget process has been used without any significant compromise of the off-state or sub-threshold characteristics. A low energy plasma enhanced chemical vapor deposition system was used to grow a thick strain-relaxation buffer in under 15 minutes before solid source MBE grew the top strained-Si layers. Strained-Si layers were grown and processed without any additional chemical mechanical polishing before device processing. The results on a relaxed technology node process suggest that strained-Si layers may be used to enhance the performance by at least one technology generation without retooling. Index terms: CMOS, pMOSFETs, strained-Si, SiGe, thermal budget, drain current enhancements, transconductance enhancements, virtual substrate.