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CPU Registers in the MSP430

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  • Msp430
  • Registers

Abstract

Connexions module: m11855 1 CPU Registers in the MSP430 ∗ CJ Ganier This work is produced by The Connexions Project and licensed under the Creative Commons Attribution License † Abstract Describes the CPU registers in the MSP430. The MSP430 has 16 CPU registers. Of these 16, the upper 12 are general purpose 16 bit registers (R4-R15). The lower four are: • R0 Program Counter(PC) � This register controls the next instruction to be executed by the MSP core. In general, this register is incremented automatically during execution. It can be used as a source in operations normally. • R1 Stack pointer (SP) � The stack pointer is used to keep track of previous execution modes and to return from interrupts. Can be read as a normal register. • R2 Status Register (SR) � The status register can be written to change the operating mode of the MSP as specified in the User's Guide. When read it can act as a constant generator. Depending on the instruction code options this register will be read as: a normal register, 0x0000, 0x0004, or 0x0008 depending on the As bits. • R3 Constant Generator II � This register cannot be written to, and when read produces: 0x0000, 0x0001, 0x0002, or 0xffff depending on the As bits. The rest of the registers on the MSP430 behave as if they were memory. In most cases, these special purpose registers can be read and written to normally; but they affect the behavior of their respective systems. ∗ Version 1.2: Aug 21, 2005 6:42 pm -0500 † http://creativecommons.org/licenses/by/1.0 http://cnx.org/content/m11855/1.2/

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