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A Methodology for Improved Verification of VLSI Designs without Loss of Area

California Institute of Technology
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  • Design


This paper describes an IC layout methodology based on arbitrary outline cells, prevention of overlap, and mixed programs and graphics. Advantages are: no loss in area over hand packing; incremental checking of design rules, component interconnection, and timing; reduction of visible complexity; and easy implementation. Disadvantages are: possible proliferation of cell types and poor handling of cells with contacts not on the boundary. An implementation that uses and enforces this methodology is discussed.

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