Abstract This paper studies the performance of a DRAM component as a function of its structure and the locality of the memory stream. We present a method and a tool for retrieving scalar values for temporal and spatial locality and discuss caches as locality filters. Combinations of cache systems and DRAM configurations having varying number of banks are simulated, and the locality of the DRAM input memory stream is analyzed. The results show that there is a usable amount of locality in the post-cache memory stream, but it is poorly utilized by the current DRAM structures. The developed scalar metrics are found to be suitable for outlining and understanding the DRAM performance. Analyzing locality and considering possibilities to utilize it by DRAMs will become essential in the future, as the DRAM row access time becomes increasingly dominant.