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A heuristic energy-aware approach for hard real-time systems on multi-core platforms

Authors
Journal
Microprocessors and Microsystems
0141-9331
Publisher
Elsevier
Volume
37
Issue
8
Identifiers
DOI: 10.1016/j.micpro.2013.04.007
Keywords
  • Dynamic Power Management
  • Dynamic Voltage And Frequency Scaling
  • Hard Real-Time Systems
  • Cluster-Based Multi-Core Processor
Disciplines
  • Computer Science
  • Design

Abstract

Abstract Due to the rapidly growing requirements of low power consumption and long battery life, the energy efficiency is becoming one of the most important concerns in the electronic system design. At the system level, the Dynamic Power Management (DPM) and Dynamic Voltage (and Frequency) Scaling (DVS) are two widely applied run-time techniques to adjust the trade-off between the system performance and power dissipation. In addition, the chip multi-core processor platforms have become the de-facto solution to cope with the continuous increase of the system complexity. In this article, we study the problem of combined application of DPM and DVS in the context of hard real-time systems on cluster-based multi-core processor platforms. We propose a heuristic algorithm based on the simulated annealing approach and introduce its online execution making the system adaptive to the run-time changes. Our approach considers multiple low power states with non-negligible state switching overhead. The experimental results show that our algorithm can significantly reduce the power consumption in comparison with existing algorithms.

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