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Statistical metrology for characterizing CMP processes

Authors
Journal
Microelectronic Engineering
0167-9317
Publisher
Elsevier
Publication Date
Volume
33
Identifiers
DOI: 10.1016/s0167-9317(96)00052-4
Keywords
  • Ii. Process Integration
Disciplines
  • Design

Abstract

Abstract CMP processes are used to planarize layers; however, variations in ILD thickness due to various layout factors can affect the modelling of interconnect parameters. In this paper an overview of ‘Statistical Metrology’ for CMP processes is presented. Using statistical metrology for CMP the process or interconnect design rules can be optimized for minimal variations.

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