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Considerations for an Analog Four Quadrant SC Multiplier

California Institute of Technology
Publication Date
  • Computer Science
  • Design


This paper outlines the considerations and design of a four quadrant analog multiplier using switched capacitor (SC) techniques. The design algorithm for accomplishing the multiplication is described. Implementation of the algorithm is then presented. The predicted accuracy of the multiplier is given and compared to preliminary breadboard measurements. The multiplier described is presently being fabricated as an integrated circuit on a university multichip project using double-poly MOS technology.

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