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Evaluating the Cost of conditional branches on the performance of superscalar machines

Authors
Journal
Microprocessing and Microprogramming
0165-6074
Publisher
Elsevier
Publication Date
Volume
38
Identifiers
DOI: 10.1016/0165-6074(93)90136-9
Disciplines
  • Computer Science

Abstract

Abstract This paper presents a study of the impact of conditional branch instructions on the performance of Superscalar processors. By interpreting non-optimised code of a real processor on various configurations derived from a Superscalar architecture model, we have evaluated the execution time percentages in which the associative dispatch algorithm remains idle, waiting for the completion of conditional branch instructions. In addition, we have assessed the volume of instruction level parallelism that can be extracted from application programs if the target machine is equipped with an omniscient branch predictor.

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