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Bit-serial SIMD on the CM-2 and the Cray-2

Authors
Journal
Journal of Parallel and Distributed Computing
0743-7315
Publisher
Elsevier
Publication Date
Volume
11
Issue
2
Identifiers
DOI: 10.1016/0743-7315(91)90119-t
Disciplines
  • Computer Science

Abstract

Abstract The term Single Instruction, Multiple Data or SIMD has been used to categorize a particular architecture in which each instruction is broadcast to a large number of processors. Each processor then executes that instruction using data local to itself. However, the SIMD concept can also be viewed as a model of computation. In this paper, two different machine architectures for supporting a SIMD programming model with one-bit granularity are investigated. One machine, the CM-2, is a bit-level parallel processor. The other machine, the Cray-2, is a vector processor with 64-bit-wide functional units that is programmed to support a bit-serial SIMD programming model. Benchmarking studies are used to compare its ability to support bit-serial SIMD to that of the CM-2.

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