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ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology

Authors
Journal
Solid-State Electronics
0038-1101
Publisher
Elsevier
Publication Date
Volume
42
Issue
11
Identifiers
DOI: 10.1016/s0038-1101(98)00167-1
Disciplines
  • Design

Abstract

Abstract A new ESD protection design by using the well-coupled field-oxide device (WCFOD) is proposed to protect the slew-rate-controlled output buffer in a 0.5 μm P-well/ N-substrate CMOS SRAM technology. The ESD transient voltage is coupled to the P-well of the ESD protection field-oxide device through a parasitic capacitor to trigger on the bipolar action of the field-oxide device. The ESD trigger voltage of the WCFOD can be lowered to below the snapback-breakdown voltage of the output NMOS transistor, so it provides effective ESD protection for the slew-rate-controlled output transistors without causing any degradation on the circuit performance. The coupling capacitor is made by inserting a poly layer right under the wire-bonding metal pad without the increase of layout area. A modified WCFOD structure is also proposed for output ESD protection in deep-submicron CMOS technology with polycide or salicide processes. Three conventional output ESD protection designs with the series resistor, the double-diode structure, and the field-oxide device, are also made for comparison. Five test chips with the same 256 K SRAM core but only different output ESD protection designs have been fabricated in a same wafer to practically verify the ESD protection efficiency of this proposed WCFOD and modified WCFOD structures.

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