Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result in harmonic distortions at the output. For different architectures of the T/H circuits, the timing error can arise from the clock random jitter or the phase skew among multi-phase clocks. For the ADC with global T/H circuits in front-end, an architecture with sine-wave sampling clock will be introduced that exhibits less random aperture jitter. First, the signal-dependent sampling error will be analyzed, and the comparison of the calculated and simulated results will be presented. Second, using the signal-to-distortion-ratio (SDR) simulations of a high speed NMOS T/H circuits with varying transition times of the sampling clock, we can compare the effects of the signal-dependent nonlinearity with other non-ideal effects. Based on the above analysis, a new architecture for multi-gigahertz sampling rate ADC using sine wave sampling will be introduced. For the ADC with time-interleaved T/Hs, a histogram based phase detector will be introduced to detect and calibrate the static timing error among the multi-channels. First, different timing error sources in high speed time-interleaved T/H will be analyzed. Second, a histogram based timing error detector will be proposed which not only cancels the skew in the multi-phase clocks but also the mismatch among different interleaved channels of the T/H circuits. An 8-channel 10GS/s T/H with timing error calibration has been implemented using IBM 90nm CMOS process. The static timing error before and after timing calibration will be presented from the measurement results.