Affordable Access

Publisher Website

Area—Time optimal VLSI integer multiplier with minimum computation time

Authors
Journal
Information and Control
0019-9958
Publisher
Elsevier
Publication Date
Volume
58
Identifiers
DOI: 10.1016/s0019-9958(83)80061-8
Disciplines
  • Design

Abstract

According to VLSI theory, [log n, √ n]is the range of computation times for which there may exist an AT 2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [ Ω(log 2 n), O(√ n)]; this theoretical question is settled, by exhibition of a class of AT 2-optimal multipliers with computation times [ Ω(log n), O(√ n)]. The designs are based on the DFT on a Fermat ring, whose elements are represented in a redundant radix-4 form to ensure O(1) addition time.

There are no comments yet on this publication. Be the first to share your thoughts.

Statistics

Seen <100 times
0 Comments

More articles like this

CMOS stuck-open self-test for an optimal-time VLSI...

on Microprocessing and Microprogr... Jan 01, 1987

Time- and VLSI-optimal convex hull computation on...

on Information Processing Letters Jan 01, 1995

AT2-optimal VLSI integer division and integer squa...

on Integration the VLSI Journal Jan 01, 1984

Multiplier-less VLSI architecture for real-time co...

on Microprocessors and Microsyste... Jan 01, 2007
More articles like this..