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Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

Authors
Journal
Journal of Electrostatics
0304-3886
Publisher
Elsevier
Publication Date
Volume
38
Identifiers
DOI: 10.1016/s0304-3886(96)00019-8
Keywords
  • Esd
  • Protection
  • Design
  • Simulation
  • Measurement

Abstract

Abstract This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and electrothermal device simulation we are able to use device-internal quantities such as the electric field or the temperature distribution to find the optimal transistor layout. Guided by simulation, we are able to guarantee a uniform avalanche breakdown of a single meander-like collector junction. Experimental results from measurements show that this is crucial for better ESD performance of a spatially efficient device. Our optimized device reaches 83% of the second breakdown trigger current of a straight device. Compared to an unoptimized meander-like device, we could increase its performance by 53%. The good agreement between measurements and simulation for different transistor shapes validates our methodology and approach to optimization of ESD devices.

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