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Active learning processes to study memory hierarchy on Multicore systems

Authors
Journal
Procedia Computer Science
1877-0509
Publisher
Elsevier
Publication Date
Volume
1
Issue
1
Identifiers
DOI: 10.1016/j.procs.2010.04.101
Keywords
  • Active Learning
  • Hierarchy Memory
  • Performance Counters
Disciplines
  • Communication
  • Computer Science

Abstract

Abstract A current challenge for computer users is to fully exploit performance of new Multicore systems. We propose a methodology for students in computational science to analyze the effect of memory hierarchy on application performance. The analysis is proposed in a experimental environment consisting of different systems with different configurations of memory hierarchy. New Multicore systems put tremendous pressure on memory hierarchy systems. The pressure is because, unfortunately, the effectiveness of the computing power offered by Multicore is affected by the data communications inter-chip and off-chip to the memory hierarchy, leading to significant problems in performance for many parallel applications. In the scope of computer science, it is important that students understand these problems. This methodology was successfully applied to students, where they acquired a significant improvement in their parallel application metrics assessment as was demonstrated in our evaluation.

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