This paper describes a Gallium Arsenide logic family called Ternary Source Coupled Fet Logic (TSCFL) that provides ternary logic elements for use in Delay Insensitive (Dl) circuits. These Dl circuits are self-timed and operate regardless of delays in wires, logic and register elements. By using ternary levels, only one wire is necessary to implement the necessary coding. The logic elements NOT, OR/AND, EXOR, and a register element have been implemented in TSCFL. A Dl FIFO ring test chip was implemented to demonstrate the potential of TSCFL for high-speed Dl circuits. Special input circuits were designed to facilitate testing, which take two high-speed binary signals and convert them, on-chip, to a high-speed ternary signal. The test circuits were implemented in the former Gigabit Logic HME/D process, and measurements show TSCFL operation up to 1.5 Gbit/s at a power dissipation of 10 mW/element. The Dl FIFO ring runs at approximately 450 Mbit/s.