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A 10-b 50-MS/s 820- μW SAR ADC With On-Chip Digital Calibration.

Authors
  • Yoshioka, Masato
  • Ishikawa, Kiyoshi
  • Takayama, Takeshi
  • Tsukamoto, Sanroku
Type
Published Article
Journal
IEEE transactions on biomedical circuits and systems
Publication Date
Dec 01, 2010
Volume
4
Issue
6
Pages
410–416
Identifiers
DOI: 10.1109/TBCAS.2010.2081362
PMID: 23850758
Source
Medline
License
Unknown

Abstract

This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm(2) .

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