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Maximizing the Effectiveness of the Ground Plane-Chapter 5

Elsevier Inc.
DOI: 10.1016/b978-075068421-7.50007-2


Publisher Summary The chapter gives an overview on maximizing the effectiveness of the ground plane. The study explains how to parallel output capacitors for proper sharing, integrated switcher IC solutions versus controller IC solutions, quick check on current through aluminum capacitors, secondary side trace inductances, and their impact on efficiency, and many more fundamentals. The study emphasizes that that there are people trying to make controller ICs with internal high-side N-Fet drivers that are not floating, but referenced to ground. These can be spotted by the fact that they have no Pin marked SW. If there is a SW node connection, it may just be there for current sensing. So no high-side driver return current passes through the SW node. The SW node is also the Source terminal of the high-side Fet (whose Gate is being held at ground). In other words, the VGS during the dead time can be about +1.5V, and can therefore turn the high-side Fet on momentarily, causing shoot-through, and loss of efficiency. To maximize the effectiveness of the ground plane, it needs to be ensured that it is the layer just below the component layer. That brings it as close to the power traces as possible. Not only does that help it couple well magnetically to the corresponding high-frequency traces above it, the increased capacitive coupling also helps sink some of the noise into the ground plane.

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