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Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

IOS Press
Publication Date
  • Communication


We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations

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