Abstract Programmable Logic Arrays (PLA) are often used in the design of VLSI circuits, because of their regular structure and flexibility. It has been reported that the major source of errors in the operation of such devices is the occurrence of soft or transient faults. Such faults can only be detected by on-line testing techniques, known as Concurrent Error Detection (CED). Most CAD tools provide a generator for automatically producing a PLA. In order to incorporate CED it is necessary to significantly modify the function. This process would be very time consuming and tedious for a designer not acquainted with all the CED techniques available. In this paper we describe a tool for the design of PLAs which incorporates CED.