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Effect of design considerations on productivity at wafer level

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
34
Issue
4
Identifiers
DOI: 10.1016/0026-2714(94)90024-8
Disciplines
  • Design

Abstract

Abstract This paper examines the effect on yield and productivity of design considerations such as packing density, levels of vertical integration, minimum design dimensions, and chip size. Expressions are presented to calculate the number of circuits on chips of different design, the initial and later yield, the time interval needed for two different products to attain the same yield, the rate of defect density reduction needed to meet a desired yield in a prescribed time period, and the productivity of different designs.

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