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A spot-defect to fault collapsing technique

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  • Design
  • Medicine


A spot-defect to fault collapsing technique - Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on A Spot-Defect to Fault Collapsing Technique Chennian Di and Jose Pineda de Gyvez Eindhoven University of Technology Department of Electrical Engineering P.O.Box 513,5600 MB, Eindhoven The Netherlands 1. Abstract Knowing the effects of process induced spot defects on an IC circuit design is very important for both IC testing and IC process diagnosis. Based on a new method of extracting "multilayer" critical areas from a circuit layout, we present a new technique capable of collapsing defects to circuit faults by establishing a simple probabilistic model between them. This way of modeling supplies accurate results for ranking the failure probability of nodes and the probability of occurrence of faults. 2. Introduction Spot defects, as a major disturbance in IC manufacturing, can cause quite complex faulty behaviors of ICs. The conventional fault models established at the gate-level, such as line stuck-at faults, are no longer sufficient when a high quality test is desired [l]. The basic problems are 1) the faults may not be physically present, and 2) the faults that occur physically may not be detected by the tests generated for such a fault model [2]. Hence, the possible faults should be extracted from their real origin: the layout, and be weighted according to the defect conditions prevailing in the manufacturing line. In normal designs, we encounter situations where more than one different defect mechanism induces the same fault, or vice versa only one defect mechanism induces more than one fault. Therefore, there is a need to perform a defect to fault collapsing in order to weight the probability of occurrence of each different fault or the probability of failure of each different node. Faults may be weighted as a function of their critical areas [3], the size(s) of the defects involved, and the corresponding defect de

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