Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)
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status: published
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations
status: published
A compact adderless feed-forward incremental ΔΣ with multiple global references for CMOS image sensors
status: Published online
Direction-of-arrival and power spectral density estimation using a single directional microphone and group-sparse optimi...
status: published
A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing
status: published
Multiple Parameter Decoupling for Resonant MEMS Sensors Exploiting Blue Sideband Excitation
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status: published
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
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Complementary field-effect transistor (CFET) has successfully boosted the area scaling of static random access memory (SRAM) bitcell due to its stacked architecture. However, this architecture introduces taller via connection from the frontside back-end-of-line (BEOL) signals to the bottom pass-gate devices, resulting in increased bitline (BL) and ...
A bagging-based selective ensemble model for churn prediction on imbalanced data
status: accepted
Modelling electricity demand in Karachi: historical trends, determinants, and future scenarios
status: published
Multiplexed superconducting qubit control at millikelvin temperatures with a low-power cryo-CMOS multiplexer
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status: Published online
