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Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

Published in Journal of Electronic Testing

As the feature size of CMOS transistors scales down, Single Event Transient (SET) has been an important consideration in designing modern radiation tolerant circuits because it may cause some failures in the circuit outputs. Many researches have been done in analyzing the impact of SET on nanometer CMOS circuits. However, it is difficult to conside...

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip

Published in Journal of Electronic Testing

Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper presents a distributed and online mechanism for detecting and locating stuck-at faults (SAFs) in NoC ch...

Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110 MHz)

Published in Journal of Electronic Testing

Nowadays, the characterization of planar integrated components is a challenge. The objective is to characterize these devices on a broadband frequency (from a few Hz to a few GHz). Currently, these integrated devices cannot be characterized at low frequencies (less than 1 MHz). This paper presents a new method and techniques for measuring integrate...

An Integrated on-Silicon Verification Method for FPGA Overlays

Published in Journal of Electronic Testing

Field Programmable Gate Arrays (FPGAs) gain popularity as higher-level tools evolve to deliver the benefits of re-programmable silicon to engineers and scientists at all levels of expertise. In order to use FPGAs efficiently, new CAD tools and modern architectures are needed for the growing demands of heterogeneous computing paradigms. Overlay arch...

Low-Cost Strategy for Bus Propagation Delay Reduction

Published in Journal of Electronic Testing

We propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very low costs in terms of area overhead, power consumption and power-delay product. Likewise some solutions adopted in industry nowadays, our strategy inserts in the bus lines repeaters implemented as a chain of inverters with increasing size. In this pa...

Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Published in Journal of Electronic Testing

In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-sc...

Editorial

Published in Journal of Electronic Testing

Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers

Published in Journal of Electronic Testing

In this paper we analyze the effect of the Bias Temperature Instability (BTI) aging phenomenon on the delay of deskew buffers employed in high performance microprocessors. Our analysis shows that, during circuit lifetime, the delay induced by BTI on each deskew buffer within the microprocessor can be significantly different, depending on how each d...