Agent
Patricia S. Goddard
Grantee
Inc. Motorola
Primary examiner
Tuan H. Nguyen
Application number
4441842
Kind
A
Document number
5578523
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Method for forming inlaid interconnects in a semiconductor device

5578523 - 4441842 - USPTO

Application May 18, 1995 - Publication Nov 26, 1996

Robert W. Fiordalice Papu D. Maniar Jeffrey L. Klein

Abstract

In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.

Description

Claims

Other sources for this patent

  • Warhead construction having an electrical ignition device

    3977330 - 4441842 - USPTO

    Application Feb 20, 1974 - Publication Aug 31, 1976

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