Applicant
Taiwan Semiconductor Manufacturing Co., Ltd.
Grantee
Taiwan Semiconductor Manufacturing Co., Ltd.
Primary examiner
Jung Kim
Application number
15485595
Kind
B2
Document number
10326430
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Low Power Flip Flop Circuit

10326430 - 15485595 - USPTO

Application Apr 12, 2017 - Publication Jun 18, 2019

Po-Chia Lai Meng-Hung Shen Chi-Lin Liu Stefan Rusu Yan-Hao Chen Jerry Chang-Jui Kao

Abstract

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

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