Agent
Margaret McNamara
Applicant
International Business Machines Corporation
Grantee
INTERNATIONAL BUSINESS MACHINES CORPORATION
Primary examiner
Binh C Tat
Application number
15586851
Kind
B2
Document number
10394994
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Field-Effect Transistor Placement Optimization for Improved Leaf Cell Routability

10394994 - 15586851 - USPTO

Application May 04, 2017 - Publication Aug 27, 2019

Iris Maria Leefken Silke Penth Michael Stetter Tobias T. Werner

Abstract

A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.

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